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IBM Reveals Its 433 Qubit Quantum Computer – EE Times

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The theme of this year’s IBM Quantum Summit, held in November, was “The Next Wave,” as IBM believes quantum is rapidly approaching an inflection point. The company hit several Quantum roadmap milestones, including the most supercomputing qubits in one system and set down a new industry challenge. During these summits, IBM updates the industry on its on-going efforts to make quantum computing a key part of the future of computing and sets goals for future developments.
One key hardware announcement was Osprey, IBM’s new 433-quantum bit (qubit) quantum processing unit (QPU) and the world’s largest superconducting quantum processor. Osprey more than triples the 127 qubits on the IBM Eagle processor, first unveiled in 2021.
Osprey is a key indicator that IBM can scale quantum processors with more qubits per chip and the company plans more growth ahead. While IBM plans to deliver over 1,000 qubits on a chip, there are limitations to scaling the number of qubits on one chip – most especially with the specialized microwave pulse controls. There’s also a size limit on the qubits before noise becomes too challenging a problem. Consequently, the ultimate future of quantum computing scaling will be to bring modularity and quantum communication for increased computational capacity.  
To control larger and multiple QPUs, IBM is developing a new 4K cryo-CMOS qubit controller that can operate down to 4°K. This microcontroller will eventually be placed within the cryostat, allowing closer control over the QPUs and reducing the signal wiring required to reach into the cryostat. IBM is building the controller with standard CMOS and has characterized the silicon operating at these very cold conditions.
In the classic “chandelier” quantum cryostats, as seen below, each layer of the cryostat runs at lower and lower temperatures until you reach the bottom, where the QPUs run at milli-Kelvin temperatures–colder than space. All levels of the cryostat also run in a vacuum because any gas would become liquid at those temperatures. In the pictures, the thin vertical cables with loops are the multiple coax cables needed to send the microwave pulses to the QPU. 
With future systems, IBM has developed a custom multilayer flex cable that sends more channels of microwave pulses to these larger QPUs and allows more efficient system assembly as the number of qubits keep growing. Running hundreds of microwave coax cables by hand is not an efficient nor reliable mechanical design. The multilayer cable, like the coax cables it replaces, must flex as the temperatures at various levels of the cryostat cause it to expand and contract. The new flex wiring provides a 70% increase in wire density and cuts the price per line by 5x. It will also improve the reliability and maintainability of the system. 
Addressing noise in quantum computers is a key barrier to the wider adoption of this technology. 
IBM released a beta update to Qiskit Runtime, which now allows a user to trade speed for reduced error count with multiple options in the API trading error rate for costs. By abstracting the complexities of these features into the software layer, developers can more easily adopt quantum computing and speed up the development of quantum applications.
As IBM Quantum Systems scale up toward the company’s goal of over 4,000 qubits by 2025 and beyond, IBM needed a next-generation system that goes beyond the current capabilities of existing physical systems and electronics. IBM provided updated details of the new IBM Quantum System Two, which is designed to be more modular and flexible. The main cryostat has changed from a cylinder to a hexagonal box. According to IBM, the six-sided design, external control electronics can be positioned next to the cryostat along with additional cryostats in a more modular design. The tradeoff is that the hexagonal box needs thicker metal construction to handle the uneven stress of the internal vacuum on the flat sides of the hexagon (whereas the internal pressure is equalized across a cylinder).
Jay Gambetta, IBM Fellow and VP of IBM Quantum, posted in a blog: “Our breakthroughs define the next wave in quantum, which we call quantum-centric supercomputing, where modularity, communication, and middleware will contribute to enhanced scaling, computation capacity, and integration of quantum and classical workflows.”  
Gambetta ended the list of summit announcements with a challenge he called “100×100.”  
The quote in his blog post: “In 2024, we plan to offer a tool capable of calculating unbiased observables of circuits with 100 qubits and 100 depth of gate operations in a reasonable runtime. We’re confident in our ability to deliver this tool, thanks to Heron: If we can build a Heron processor with error rates below the “three-nines” gate fidelity threshold, plus the software infrastructure to read out the circuits in concert with classical resources, then we can run a circuit of 100×100 in less than a day and produce unbiased results. ​This system will be able to run quantum circuits with complexity and runtime beyond the capabilities of the best classical computers today.” 
At that threshold, IBM believes it will be able to demonstrate that quantum computers can solve problems that are impractical on classical computers, often called Quantum Advantage. Having QPUs with more than 100 nearly error-free qubits allows the implementation of deeper circuits and therefore more complex operations. 
One participant offered this maxim: “If you’re early, you’re on time; if you’re on time, you’re late.” 
The early adopters of quantum computing are developing capabilities that they hope will pay benefits in the future. We’re still not sure where quantum computing will gain early traction, where it will get the best results, but TIRIAS Research believes that early exploration and pathfinding will surely benefit the explorers including IBM.
 

Kevin Krewell is Principal Analyst at Tirias Research. Before joining Tirias Research, he was a Senior Analyst at The Linley Group and a Senior Editor of Microprocessor Report. He spent nine years at MPR in a variety of roles, contributing numerous articles on mobile SoCs, PC processors, graphics processors, server processors, CPU IP cores, and related technology. For The Linley Group, he co-authored reports that analyzed market positioning and technical features of the various vendor products. He has more than 25 years of industry experience in both engineering and marketing positions. Before joining The Linley Group, Kevin was Director of Strategic Marketing at Nvidia and Director of Technical Marketing at Raza Microelectronics (now part of Broadcom). He spent more than a decade at AMD in various roles, including technical marketing manager and field application engineer. He also understands the needs of engineers, having spent 10 years in product design at several smaller companies. He earned a BS in electrical engineering from Manhattan College. He also holds an MBA from Adelphi University and is a member of the IEEE as well as a member of the Microprocessor Oral History SIG for the Computer History Museum.


Kevin Krewell is Principal Analyst at Tirias Research. Before joining Tirias Research, he was a Senior Analyst at The Linley Group and a Senior Editor of Microprocessor Report. He spent nine years at MPR in a variety of roles, contributing numerous articles on mobile SoCs, PC processors, graphics processors, server processors, CPU IP cores, and related technology. For The Linley Group, he co-authored reports that analyzed market positioning and technical features of the various vendor products. He has more than 25 years of industry experience in both engineering and marketing positions. Before joining The Linley Group, Kevin was Director of Strategic Marketing at Nvidia and Director of Technical Marketing at Raza Microelectronics (now part of Broadcom). He spent more than a decade at AMD in various roles, including technical marketing manager and field application engineer. He also understands the needs of engineers, having spent 10 years in product design at several smaller companies. He earned a BS in electrical engineering from Manhattan College. He also holds an MBA from Adelphi University and is a member of the IEEE as well as a member of the Microprocessor Oral History SIG for the Computer History Museum.
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