Since 1987 – Covering the Fastest Computers in the World and the People Who Run Them
Since 1987 – Covering the Fastest Computers in the World and the People Who Run Them
December 9, 2021
SCANDIANO, Italy, Dec. 9, 2021 — E4 Computer Engineering builds on 20+ years of developing and integrating innovative technologies and announces Monte Cimone, a cluster aimed at enabling the co-design of high performance scientific and engineering applications and the supporting software stack on RISC-V.
DEI-UNIBO, the Electric, Electronic and Information Engineering “Guglielmo Marconi” department of the Università di Bologna, has contributed to Monte Cimone’s system architecture definition, software stack development and integration within the Examon data-center automation environment.
CINECA, the leading italian supercomputing center, has ported high-performance mathematical libraries (OpenBLAS, FFTW, Netlib-LAPACK, Netlib-scaLAPACK) and scientific applications (HPL, Quantum Espresso) against the RISC-V ISA supporting E4 and Università di Bologna in the validation of the components of the cluster in the operational environment.
Monte Cimone is currently undergoing the final validation tests at DEI-UNIBO and a similar architecture, albeit at a smaller scale, is located at E4’s R&D lab for further developments.
Once fully validated at DEI-UNIBO and at E4, Monte Cimone will be relocated at CINECA for further testing and for its integration in CINECA’s exascale-class compute environment.
Monte Cimone is the first RISC-V ISA cluster specifically designed, built, and validated for co-design activities targeted to enable its use in the HPC ecosystem and having an operational environment as the primary target. Monte Cimone enables developers to test and validate scientific and engineering workloads in a rich software stack, including development tools, libraries for message-passing programming, BLAS, FFT, drivers for HS networks and I/O devices. The objective is to achieve a future-ready position capable of addressing and leveraging the features of the RISC-V ISA for scientific and engineering applications and workloads in an operational environment. The continuous dialogue between E4, DEI-UNIBO and CINECA enabled Monte Cimone to achieve such a level of stability and reliability, both in term of HW and SW, to run various workflows (e.g. Quantum Espresso) and enabling further applications to be ported.
The key hardware components of Monte Cimone are:
RISC-V is a very promising ISA for HPC. The European Processor Initiative will use a RISC-V based accelerator. An intense development effort is taking place these days to gauge the maturity of the current generation of RISC-V based processors with the most intense HPC workload. Prof. Luca Benini (DEI-UNIBO), a key member of the EPI consortium and a driving force behind the development of RISC-V, proposed E4 and CINECA to begin a development process that would eventually become Monte Cimone.
Monte Cimone will be used as a platform for porting and tuning HPC-relevant software stacks and HPC applications to the RISC-V architecture. The hardware will be further extended by adding PCEe acceleration cards to explore heterogeneous architectures and based on RISC-V. Complementing the rich set of HW components, the porting of the Infiniband stack is ongoing and will be added to the current configuration as soon as validated. The modularity of the cluster architecture will enable its extensions with new blades hosting higher performance RISC-V processors, memories and storage components as they will become available on the market.
Monte Cimone has an elevation of 2,165 m and is the highest point in the Emilia-Romagna region of Italy, where E4, Università di Bologna and CINECA are located. It is a winter ski resort frequented by snowboarders as it hosts a large snowpark.
Cosimo Gianfreda, CTO of E4 Computer Engineering: “Over the years, E4 has pursued the strategy to be at the leading edge of innovative technology. Our products have been designed considering the requirements of the end users and with the goal to make these systems user-friendly while providing top performance at the lowest TCO. Monte Cimone represents a key opportunity for co-designing and developing innovative RISC-V based technologies and is a significant leap in proposing high-tech and energy energy-efficient solutions.”
“I am extremely excited by the results we achieved with Monte Cimone, which demonstrate remarkable maturity of the RISC-V software stack and tools for HPC. I believe that RISC-V based HPC machines are not far, and Monte Cimone will be instrumental to get there faster”, says Prof. Luca Benini, Full professor of Electronics at DEI-UNIBO and Chair of Digital Circuits and Systems at ETH Zurich.
Dr. Daniele Cesarini, HPC Specialist at CINECA: “As a supercomputing center, we are very interested in the RISC-V technology to support the scientific community. We are excited to contribute to the RISC-V ecosystem supporting the installation and tuning of widely-used scientific codes and mathematical libraries to push forward the development of high-performance RISC-V CPUs. We believe that Monte CIMONE will be the harbinger of the next generation of supercomputers based on RISC-V technology and we will continue to work in synergy with E4 Computer Engineering and the Università di Bologna to prove that RISC-V is ready to stay on the shoulder of the HPC giants.”
About E4 Computer Engineering
E4 Computer Engineering creates and supplies hardware and software solutions for High Performance Computing, Cloud Computing (Private and Hybrid), containerization, High Performance Data Analytics, Artificial Intelligence, Deep Learning and Virtualization. The growth of recent years has led the company to complete its offer with the inclusion of various open-source technologies such as OpenStack, Kubernetes, and tools for the implementation of a CI / CD toolchain. www.e4company.com
About CINECA
Cineca, established in 1969, is a non-profit consortium of 70 Italian Universities, 9 national research institution, and the Ministry of University and Research (MUR). Cineca is the largest Italian supercomputing center with an HPC environment equipped with cutting-edge technology and highly-qualified personnel which cooperates with researchers in the use of the HPC infrastructure, in both the academic and industrial fields. Cineca’s mission is to enable the Italian and European research community to accelerate the scientific discovery using HPC resources in a profitable way, exploiting the newest technological advances in HPC, data management, storage systems, tools, services and expertise at large. www.hpc.cineca.it.
About Università di Bologna
Università di Bologna (UNIBO) is the oldest university in the western world and the top-ranked generalist university in Italy (QS World University Rankings 2022). DEI, the Electric, Electronic and Information Engineering “Guglielmo Marconi” department is top-three ranked in Italy (subject: Electrical Engineering). DEI has collaborated for more than a decade with E4 and CINECA to the co-development of energy-efficient supercomputers. DEI researchers have developed Examon, a state-of the art tool for holistic management of HPC systems and have contributed to the RISC-V open ecosystem since its inception. www.dei.unibo.it.
Source: E4 Computer Engineering
More Off The Wire
Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!
December 27, 2021
Today, the LLVM compiler infrastructure world is essentially inescapable in HPC. But back in the 2000 timeframe, LLVM (low level virtual machine) was just getting its start as a new way of thinking about how to overcome Read more…
December 21, 2021
Call it a New Year’s resolution: the EuroHPC Joint Undertaking—which serves as the concerted supercomputing play of the European Union—has issued a new call for a tender as it restarts the procurement process for t Read more…
December 21, 2021
Decoding the replication mechanisms of the SARS-CoV-2 virus has been a key research quest as the COVID-19 pandemic continues. For the scientific computing world, creating accurate models of how the virus replica Read more…
December 21, 2021
Nvidia today reported its BlueField-2 DPU delivered 41.5M IOPS on a storage benchmarking test and declared that it delivers “more than 4x more IOPS than any other DPU.” Nvidia issued the claim to counter last month’s Read more…
December 20, 2021
Photovoltaic solar – what most people know as solar panels – generated a record 821 terawatt-hours in 2020, a 23 percent increase over 2019 and an impressive 3.1 percent of global electricity generation. But with cli Read more…
High performance computing (HPC) helps researchers, engineers and academic institutions to process simulations that are too complex to resolve within an acceptable timeframe or are just too large, which warrants a distribution of the workload across many servers. Read more…
December 17, 2021
2021 marked the 18th annual HPCwire Readers’ and Editors’ Choice Awards. Coming off a tumultuous 2020, this year marked something of a return to normalcy: many supercomputing centers that had backburnered their day-t Read more…
December 27, 2021
Today, the LLVM compiler infrastructure world is essentially inescapable in HPC. But back in the 2000 timeframe, LLVM (low level virtual machine) was just getti Read more…
December 21, 2021
Call it a New Year’s resolution: the EuroHPC Joint Undertaking—which serves as the concerted supercomputing play of the European Union—has issued a new ca Read more…
December 21, 2021
Nvidia today reported its BlueField-2 DPU delivered 41.5M IOPS on a storage benchmarking test and declared that it delivers “more than 4x more IOPS than any o Read more…
December 20, 2021
Photovoltaic solar – what most people know as solar panels – generated a record 821 terawatt-hours in 2020, a 23 percent increase over 2019 and an impressiv Read more…
December 17, 2021
2021 marked the 18th annual HPCwire Readers’ and Editors’ Choice Awards. Coming off a tumultuous 2020, this year marked something of a return to normalcy: m Read more…
December 16, 2021
As Intel, HPE, and Argonne National Laboratory drive toward a 2022 delivery of the Aurora leadership-class supercomputer, HPCwire spoke with Dr. Robert Wisniewski, Intel Fellow: SuperCompute Software, Aurora technical lead and PI, to learn about Intel’s Borealis testbed for Aurora. Wisniewski also explains why he views High Bandwidth Memory as a game-changer for HPC. Read more…
December 14, 2021
Earlier this month, the Intelligence Advanced Research Projects Activity (IARPA) and the U.S. Army Combat Capabilities Development Command’s Army Research issued a call for proposals to build a new computer architecture to handle the growing flood of data. “Clean sheet designs are needed to address today’s era of explosive data growth,” said IARPA AGILE program manager, William Harrod. “ Read more…
December 14, 2021
Rockport Networks, a new entrant in the HPC networking space with its switchless fabric offering, today announced the appointment of Marc Sultzbaugh to co-CEO. An active Rockport board member since December 2020, Sultzbaugh will lead the company alongside Rockport Networks Co-Founder and Co-CEO Doug Carwardine. Sultzbaugh previously spent 20 years at HPC networking company Mellanox… Read more…
November 3, 2021
On October 1 of this year, IonQ became the first pure-play quantum computing start-up to go public. At this writing, the stock (NYSE: IONQ) was around $15 and its market capitalization was roughly $2.89 billion. Co-founder and chief scientist Chris Monroe says it was fun to have a few of the company’s roughly 100 employees travel to New York to ring the opening bell of the New York Stock… Read more…
September 29, 2021
At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership… Read more…
November 8, 2021
At a virtual event this morning, AMD CEO Lisa Su unveiled the company’s latest and much-anticipated server products: the new Milan-X CPU, which leverages AMD’s new 3D V-Cache technology; and its new Instinct MI200 GPU, which provides up to 220 compute units across two Infinity Fabric-connected dies, delivering an astounding 47.9 peak double-precision teraflops. “We’re in a high-performance computing megacycle, driven by the growing need to deploy additional compute performance… Read more…
October 15, 2021
Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing… Read more…
October 21, 2021
AMD’s next-generation supercomputer GPU is on its way – and by all appearances, it’s about to make a name for itself. The AMD Radeon Instinct MI200 GPU (a successor to the MI100) will, over the next year, begin to power three massive systems on three continents: the United States’ exascale Frontier system; the European Union’s pre-exascale LUMI system; and Australia’s petascale Setonix system. Read more…
October 21, 2021
Earlier this month D-Wave Systems, the quantum computing pioneer that has long championed quantum annealing-based quantum computing (and sometimes taken heat fo Read more…
November 24, 2021
Details about two previously rumored Chinese exascale systems came to light during last week’s SC21 proceedings. Asked about these systems during the Top500 media briefing on Monday, Nov. 15, list author and co-founder Jack Dongarra indicated he was aware of some very impressive results, but withheld comment when asked directly if he had… Read more…
September 22, 2021
The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…
November 18, 2021
Today at the hybrid virtual/in-person SC21 conference, the organizers announced the winners of the 2021 ACM Gordon Bell Prize: a team of Chinese researchers leveraging the new exascale Sunway system to simulate quantum circuits. The Gordon Bell Prize, which comes with an award of $10,000 courtesy of HPC pioneer Gordon Bell, is awarded annually… Read more…
September 13, 2021
What is one to make of the quantum computing market? Energized (lots of funding) but still chaotic and advancing in unpredictable ways (e.g. competing qubit tec Read more…
September 8, 2021
IBM today introduced the Power E1080 server, its first system powered by a Power10 IBM microprocessor. The new system reinforces IBM’s emphasis on hybrid cloud markets and the new chip beefs up its inference capabilities. IBM – like other CPU makers – is hoping to make inferencing a core capability… Read more…
January 13, 2021
The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…
December 27, 2021
Today, the LLVM compiler infrastructure world is essentially inescapable in HPC. But back in the 2000 timeframe, LLVM (low level virtual machine) was just getti Read more…
September 23, 2021
As Moore’s law slows, HPC developers are increasingly looking for speed gains in specialized code and specialized hardware – but this specialization, in turn, can make testing and deploying code trickier than ever. Now, researchers from Texas A&M University, the University of Illinois at Urbana… Read more…
June 1, 2020
The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…
November 15, 2021
No exascale for you* — at least, not within the High-Performance Linpack (HPL) territory of the latest Top500 list, issued today from the 33rd annual Supercomputing Conference (SC21), held in-person in St. Louis, Mo., and virtually, from Nov. 14–19. “We were hoping to have the first exascale system on this list but that didn’t happen,” said Top500 co-author… Read more…
© 2021 HPCwire. All Rights Reserved. A Tabor Communications Publication
HPCwire is a registered trademark of Tabor Communications, Inc. Use of this site is governed by our Terms of Use and Privacy Policy.
Reproduction in whole or in part in any form or medium without express written permission of Tabor Communications, Inc. is prohibited.
